Semiconductor memory device

ABSTRACT

A semiconductor memory device includes word lines, drain lines, source lines, a memory array including plural memory cells formed from a field effect transistor, a data write circuit, a write control circuit, and a word line drive circuit, wherein the write control circuit outputs the drain drive voltage of H-level to the selected memory cell when a data write operation is commanded, and outputs the drain drive voltage of L-level when a data write operation is not commanded, and the data write circuit generates a write voltage corresponding to a logical value of data to be written into the selected memory cell based on the drain drive voltage outputted from the write control circuit, and supplies the write voltage as the source drive voltage via the source line to the selected memory cell when a data write operation is commanded by the first control signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device such as anon-volatile memory (e.g., an EPROM) which allows electrical write.

2. Description of the Related Art

FIG. 16 is a diagram schematically showing the construction of aconventional EPROM. See Japanese Patent Kokai (Laid-Open) PublicationNo. 2000-331486, for example. Further, FIG. 17 is a diagramschematically showing the construction of four memory cells in the EPROMof FIG. 16. Furthermore, FIGS. 18 and 19 are diagrams for describing theproblems in the EPROM of FIG. 16.

The EPROM shown in FIG. 16 has memory arrays 10 ₀, . . . , 10 _(n)provided with plural memory cells 11 (in distinguishing and describingeach, the symbols 11 a, 11 b, 11 c and 11 d are also used) formed in asemiconductor substrate. In the semiconductor substrate in which thememory arrays 10 ₀, . . . , 10 _(n) on are formed, plural word linesWL₀, . . . , WL_(n) are arranged mutually in parallel, plural drainlines DL₀, . . . , DL_(y), DL_(z) are arranged intersectingperpendicularly with the word lines WL₀, . . . , WL_(n), and pluralsource lines SL₀, . . . , SL_(y), SL_(z) are arranged intersectingperpendicularly with the word lines WL₀, . . . , WL_(n). As shown inFIG. 17, the memory cell 11 (11 a, 11 b, 11 c and 11 d) includes, forexample, field effect transistors which have gates GA, drains DR_(a),DR_(bc) and DR_(d), sources SOU_(ab) and SOU_(cd), and floating gatesFG_(a), FG_(b), FG_(c) and FG_(d). The gates of the plural memory cells11 are connected to one of the plural word lines WL₀, . . . , WL_(n).Each drain of the plural memory cells 11 is connected to one of theplural drain lines DL₀, . . . , DL_(z), and each source of the pluralmemory cells 11 is connected to one of the plural source lines SL₀, . .. , SL_(z). In addition, the actual EPROM has circuits such as anaddress decoder for generating decoded signals DEC₀, . . . , DEC_(n),and a sense amplifier to read the data stored in the memory cell, thesenot being shown in the figures.

In each of the memory arrays 10 ₀, . . . , 10 _(n), the drain lines DL₀,. . . , DL_(y), DL_(z) are respectively connected via NMOS transistors12 ₀, . . . , 12 _(y1) (or 12 _(y2)), 12 _(z1) (or 12 _(z2)) to a writecontrol line 13, to which a drain drive voltage (write control signal)MCD is supplied. In each of the memory arrays 10 ₀, . . . , 10 _(n),ON/OFF control of the even-numbered NMOS transistors 12 ₀, 12 ₂, . . . ,12 _(y1), 12 _(z1) is performed by even number selection signals SE₀, .. . , SE_(n), respectively, and ON/OFF control of the odd-numbered NMOStransistors 12 ₁, 12 ₃, . . . , 12 _(y2), 12 _(z2) is performed by oddnumber selection signals SO₀, . . . , SO_(n), respectively. Moreover, ineach of the memory arrays 10 ₀, . . . , 10 _(n), the source lines SL₀, .. . , SL_(y), SL_(z) are connected to the bit lines BL₀, . . . , BL_(y),BL_(z) via the NMOS transistors 14 ₀, . . . 14 _(y), 14 _(z) which areON/OFF controlled by memory array selection signals SS₀, . . . , SS_(n).

The EPROM shown in FIG. 16 includes word line drive circuits 20 ₀, . . ., 20 _(n) which supply drive signals to each of the word lines WL₀, . .. , WL_(n), a write control circuit 30 which supplies the drain drivevoltage MCD to the write control line 13, data write circuits 40 ₁ and40 ₂ which supply data BLA₁ and BLA₂ (data supplied to the bit linesBL_(y) and BL_(z) are represented as BLA₃ and BLA₄, respectively) to thebit lines BL₀, . . . , BL_(y), BL_(z) (the data write circuits 40 ₃ and40 ₄ supply data BLA₃ and BLA₄ to the bit lines BL_(y) and BL_(z),respectively), and a delay circuit 50 which delays a reset signal RSTand outputs the delayed reset signal as a reset signal RST₁. The inputof the data write circuits 40 ₃ and 40 ₄ is a power supply voltage VCCwhich is at high level (H-level).

The word line drive circuits 20 ₀, . . . , 20 _(n) have mutuallyidentical constructions. The word line drive circuits 20 ₀, . . . , 20_(n) respectively generate and output word line selection signals (wordline drive voltages) to be supplied to the word lines WL₀, . . . ,WL_(n) in accordance with the decoded signals DEC₀, . . . , DEC_(n)supplied from the address decoder. When the decoded signals DEC₀, . . ., DEC_(n) are at low level (L-level) which represents “non-selection”,the word line drive circuits 20 ₀, . . . , 20 _(n) output a groundvoltage GND to the word lines WL₀, . . . , WL_(n) as a word lineselection signal. When the decoded signals DEC₀, . . . , DEC_(n) are atH-level which represents “selection”, the word line drive circuits 20 ₀,. . . , 20 _(n) function according to a program mode signal “^(˜)PGM”(in this specification, “^(˜)PGM” means “PGM” with an upper line (i.e.,overline), and represents the inverse signal of the signal PGM. In thefigures, “^(˜)PGM” is represented as “PGM” with an upper line. Duringdata write, the word line drive circuits 20 ₀, . . . , 20 _(n) output aprogram voltage VPP (e.g., 10 V) to the word lines WL₀, . . . , WL_(n)as a word line selection signal, and during data read, output the powersupply voltage VCC to the word lines WL₀, . . . , WL_(n) as a word lineselection signal.

During data write, the reset signal RST inputted to the write controlcircuit 30 is at L-level, the drain drive voltage MCD outputted from thewrite control circuit 30 is determined by the program voltage VPP andthe control voltage VR, and is a voltage VCC+2Vtn (where Vtn is athreshold voltage of the NMOS transistor, and is approximately 1 V). Thereset signal RST is at H-level during data read. At this time, the draindrive voltage MCD outputted from the write control circuit 30 is theground voltage GND.

The data write circuits 40 ₁, 40 ₂, 40 ₃ and 40 ₄ have mutuallyidentical constructions. When the program mode signal ^(˜)PGM is causedto be L-level to perform a data write operation, the data write circuits40 ₁ and 40 ₂ output the ground voltage GND or the write signals BLA₁and BLA₂ of the power supply voltage VCC from a node N40 according tothe L-level or H-level of input data D₁ and D₂. The data write circuits40 ₁, 40 ₂, 40 ₃ and 40 ₄ are configured in such a way that when a dataread operation is performed by the program mode signal ^(˜)PGM, the nodeN40 of the data write circuits 40 ₁ and 40 ₂ is in a high impedancestate.

For example, the data write circuit 40 ₁ includes an inverter 41 towhich the input data D₁ is supplied, a NOR gate 42 which outputs thenegative logical sum of the output signal of the inverter 41 and theprogram mode signal ^(˜)PGM, and a NOR gate 43 which outputs thenegative logical sum of the output signal of the NOR gate 42 and theprogram mode signal ^(˜)PGM. The data write circuit 40 ₁ also includesan NMOS transistor 44 which is connected between the node N40 and theground voltage GND, and is controlled by the output signal of the NORgate 43, an NMOS transistor 45 which is connected between the powersupply voltage VCC and the node N40, and is controlled by the outputsignal of the NOR gate 42, and an NMOS transistor 46 which is connectedbetween the node N40 and the ground voltage GND, and is controlled bythe reset signal RST₁ outputted from the delay circuit 50.

The write signals BLA₁ and BLA₂ outputted from the data write circuit 40₁ and 40 ₂ are respectively supplied, for example, to the adjacent bitlines BL₀ and BL₁ via the transistors 60 a and 60 b selected by columnselection signals Y₀ and Y₁.

When a logical value low (represented by ‘L’) is written as data intothe memory cell 11 selected by the word line WL_(i) (a subscript “i” isan integer from 0 to n) even number selection signal SE_(j) or the oddnumber selection signal SO_(j) (a subscript “j” is an integer from 0 ton), memory array selection signal SS_(j), and column selection signalY_(k) (a subscript “k” is an integer greater than 0), the data D₁inputted to the data write circuit 40, is at L-level. At this time, thegate voltage Vg of the memory cell 11 is 10 V, the drain voltage Vd isVCC+2Vtn (=6 V), and the source voltage Vs is 0 V. Therefore, in thememory cell 11, a large current I_(a1) flows from the drain to thesource (e.g., in FIG. 17, from the drain DR_(a) to the source SOU_(ab)),and due to the avalanche hot carrier generated by this current,electrons are injected into the floating gate (e.g., in FIG. 17, thefloating gate FG_(a)).

On the other hand, when a high logical value (represented by ‘H’) iswritten as data into the memory cell 11 selected by the word lineWL_(i), even number selection signal SE_(j) or odd number selectionsignal SO_(j), memory array selection signal SS_(j) and column selectionsignal Y_(k), the input data D₂ is at H-level. At this time, the gatevoltage Vg of the memory cell 11 is 10 V and the drain voltage Vd isVCC−2Vtn (=3 V). Therefore, in the memory cell 11, only a relativelysmall current I_(d1) flows from the drain to the source (e.g., in FIG.17, from the drain DR_(d) to the source SOU_(cd)), and electrons are notinjected into the floating gate (e.g., in FIG. 17, the floating gateFG_(d)) because no avalanche hot carriers are generated.

In the aforesaid conventional EPROM, two adjacent bit lines BL_(k) andBL_(k+1) are selected simultaneously by the column selection signalY_(k). The data (e.g., data BLA₁ and BLA₂) outputted from the data writecircuits (e.g., data write circuits 40 ₁ and 40 ₂) are writtenrespectively into two memory cells 11 connected to the selected bitlines BL_(k) and BL_(k+1). In FIG. 16, the data BLA₁ and BLA₂ arewritten simultaneously into the memory cells 11 a and 11 d selected bythe word line WL₀, even number selection signal SE₀, memory arrayselection signal SS₀, and the column selection signal Y₀, respectively.For example, if the memory cell 10 ₀ is selected by the memory arrayselection signal SS₀, the word line WL₀ is selected by the word linedrive circuit 20 _(n), the bit lines BL₀ and BL₁ are selected by thecolumn selection signal Y₀, and the drain lines DL₀ and DL₂ are selectedby the even number selection signal SE₀, current flows from the drainline DL₀ via the memory cell 11 a, source line SL₀, NMOS transistor 14₀, and bit line BL₀. As a result, a charge accumulates in the floatinggate of the memory cell 11 a (when it has the logical value ‘L’), ordoes not accumulate in it (when it has the logical value ‘H’). Also,current flows from the drain line DL₂ via the memory cell 11 d, sourceline SL₁, NMOS transistor 141, and bit line BL₁. As a result, a chargeaccumulates in the floating gate of the memory cell 11 d (when it hasthe logical value ‘L’), or does not accumulate in it (when it has thelogical value ‘H’).

In the above-mentioned conventional EPROM, the program mode signal^(˜)PGM inputted to the data write circuits 40 ₁ and 40 ₂ is at H-level,the outputs of the NOR gates 42 and 43 are at L-level, and then the NMOStransistors 44 and 45 are both OFF. As a result, the output (namely, thenode N40) of the data write circuits 40 ₁ and 40 ₂ is in a highimpedance state. At this time, a current path from the memory cells 11a, 11 b, 11 c and 11 d to the ground voltage GND does not exist, so ifthe memory cells 11 a, 11 b, 11 c and 11 d are in the logical value ‘H’state, as shown in FIG. 18, the drain lines DL₀, DL₁ and DL₂, the sourcelines SL₀ and SL₁, and the bit lines BL₀ and BL₁ go up to the draindrive voltage MCD, i.e., VCC+2Vtn, (=6 V) via the memory cells 11 a, 11b, 11 c and 11 d, respectively.

Here, if the logical value ‘L’ is written into the memory cell 11 a andthe logical value ‘H’ is written into the memory cell 11 d, the programmode signal ^(˜)PGM inputted to the data write circuits 40 ₁ and 40 ₂ isat L-level, the write signal BLA₁ outputted from the data write circuit40, is at L-level, and the write signal BLA₂ outputted from the datawrite circuit 40 ₂ is at H-level. Then, as shown in FIG. 19, the bitline BL₀ and source SOU_(ab) are at ground voltage GND (=0 V), and thebit line BL₁ and source SOU_(cd) are at a voltage VCC−Vtn (=3 V). Atthis time, as shown by the arrow I_(a2), current flows from the drainDR_(a) to the source SOU_(ab) at GND voltage, electrons are injectedinto the floating gate FG_(a) by an avalanche hot carrier, and thelogical value ‘L’ is written into the memory cell 11 a. Also, only asmall current I_(d2) flows from the drain DR_(d) to the source SOU_(cd)at the voltage VCC−Vtn, so electrons are not injected into the floatinggate FG_(d) by an avalanche hot carrier, and the logical value ‘H’ iswritten into the memory cell 11 d.

However, before data write to the memory cells 11 a and 11 d shown inFIG. 19 (at a time shown in FIG. 18), when data write occurs, the charge(voltage VCC+2Vtn) stored in the bit line BL₁ and drain line DL₁ isdischarged through the source line SL₀ and bit line BL₀ at GND level,e.g., via the memory cell 11 b. Due to this discharge current (e.g.,current I_(b) in FIG. 19), electrons may be injected into the floatinggate FG_(b) of the memory cell 11 b, and incorrect write of data to thememory cell 11 b which is not selected, may arise. Moreover, if thethreshold voltage Vt of the memory cell increases due to injection ofelectrons into the floating gate, an access delay may occur and theoperating power supply voltage may change.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide asemiconductor memory device which does not cause incorrect data write oran access delay.

According to the present invention, a semiconductor memory deviceincludes plural word lines; plural drain lines; plural source lines; amemory array including plural memory cells formed from a field effecttransistor having a gate, a drain, a source and a floating gate, thegate of each of the plural memory cells being connected to any of theplural word lines, the drain of each of the plural memory cells beingconnected to any of the plural drain lines, the source of each of theplural memory cells being connected to any of the plural source lines; adata write circuit which receives a first control signal and write dataand supplies a source drive voltage to the source line when data iswritten into the memory cell; a write control circuit which receives asecond control signal supplied later than the first control signal andsupplies a drain drive voltage based on the second control signal to thedrain line when data is written into the memory cell; and a word linedrive circuit which receives an address signal and the second controlsignal, and supplies a word line drive voltage based on the secondcontrol signal to the word line selected according to the addresssignal. The write control circuit outputs the drain drive voltage at ahigh level for data write via the drain line to the memory cell selectedby the word line drive circuit when a data write operation is commandedby the second control signal, and outputs the drain drive voltage at alow level when a data write operation is not commanded by the controlsignal, and the data write circuit generates a write voltagecorresponding to a logical value of data to be written into the selectedmemory cell based on the drain drive voltage outputted from the writecontrol circuit, and supplies the write voltage as the source drivevoltage via the source line to the selected memory cell when a datawrite operation is commanded by the first control signal.

According to the present invention, a second control signal which has adelayed timing with respect to a first control signal (program modesignal) which commands a data write operation, is supplied to a wordline drive circuit and a control circuit, and a high level controlvoltage for data write generated by the write control circuit issupplied to a data write circuit. Hence, when the data to be written issupplied to the data write circuit, in a selected memory cell andanother memory cell which is not selected, the voltage of the drain andsource is essentially ground voltage. Subsequently, a high levelselection signal for data write is outputted from the word line drivecircuit by a second control signal, and a high level control voltage fordata write is generated by the write control circuit, and supplied tothe data write circuit. Therefore, a high voltage is no longer appliedbetween the drain and source of memory cells into which data are notwritten, and the cause of incorrect writes and fluctuation in thethreshold voltage of the memory cells is eliminated.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will become more fully understood from thedetailed description given hereinbelow and the accompanying drawingswhich are given by way of illustration only, and thus are not limitativeof the present invention, and wherein:

FIG. 1 is a diagram schematically showing the construction of an EPROMaccording to a first embodiment of the present invention;

FIG. 2 is a signal waveform diagram for describing a data writeoperation of the EPROM according to the first embodiment;

FIG. 3 is a diagram (No. 1) for describing a data write operation of theEPROM according to the first embodiment;

FIG. 4 is a diagram (No. 2) for describing a data write operation of theEPROM according to the first embodiment;

FIG. 5 is a diagram (No. 3) for describing a data write operation of theEPROM according to the first embodiment;

FIG. 6 is a diagram schematically showing the construction of the EPROMaccording to a second embodiment of the present invention;

FIG. 7 is a signal waveform diagram for describing a data writeoperation of the EPROM according to the second embodiment;

FIG. 8 is a diagram schematically showing the construction of an EPROMaccording to a third embodiment of the present invention;

FIG. 9 is a circuit diagram showing the construction of a control signalgeneration circuit of the EPROM according to the third embodiment;

FIG. 10 is a diagram schematically showing the construction of an EPROMaccording to a fourth embodiment of the present invention;

FIG. 11 is a circuit diagram showing the construction of the data writecircuit of the EPROM according to the fourth embodiment;

FIG. 12 is a signal waveform diagram for describing a data writeoperation of the EPROM according to the fourth embodiment;

FIG. 13 is a diagram (No. 1) for describing a data write operation ofthe EPROM according to the fourth embodiment;

FIG. 14 is a diagram (No. 2) for describing a data write operation ofthe EPROM according to the fourth embodiment;

FIG. 15 is a diagram (No. 3) for describing a data write operation ofthe EPROM according to the fourth embodiment;

FIG. 16 is a diagram schematically showing the construction of a priorart EPROM;

FIG. 17 is a diagram schematically showing the construction of memorycells of a conventional EPROM;

FIG. 18 is a diagram (No. 1) for describing a problem of theconventional EPROM; and

FIG. 19 is a diagram (No. 2) for describing a problem of theconventional EPROM.

DETAILED DESCRIPTION OF THE INVENTION

Further scope of applicability of the present invention will becomeapparent from the detailed description given hereinafter. However, itshould be understood that the detailed description and specificexamples, while indicating preferred embodiments of the invention, aregiven by way of illustration only, since various changes andmodifications will become apparent to those skilled in the art from thedetailed description.

First Embodiment

FIG. 1 is a diagram schematically showing the construction of an EPROMwhich is a semiconductor memory device according to the first embodimentof the present invention. Those structures in FIG. 1 that are identicalto or correspond to structures in FIG. 16 are assigned identicalsymbols. Further, FIG. 2 is a signal waveform diagram for describing adata write operation of the EPROM according to the first embodiment.Furthermore, FIGS. 3 to 5 are diagrams (Nos. 1-3) for describing a datawrite operation of the EPROM according to the first embodiment.

The EPROM according to the first embodiment includes memory arrays 10 ₀,. . . , 10 _(n) provided with plural memory cells 11 (in distinguishingand describing each, the symbols 11 a, 11 b, 11 c and 11 d will also beused) formed in a semiconductor substrate. The region on thesemiconductor substrate in which the memory arrays 10 ₀, . . . , 10 _(n)are formed is provided with plural word lines WL₀, . . . , WL_(n),plural drain lines DL₀, . . . , DL_(y), DL_(z), and plural source linesSL₀, . . . , SL_(y), SL_(z).

The memory cells 11 (11 a, 11 b, 11 c and 11 d) are field effecttransistors which have gates (e.g., gates GA in FIG. 3), drains (e.g.,drains DR_(a), DR_(bc) and DR_(d) in FIG. 3), sources (e.g., sourcesSOU_(ab) and SOU_(cd) in FIG. 3), and floating gates (e.g., FG_(a),FG_(b), FG_(c) and FG_(d) in FIG. 3).

The gates of the plural memory cells 11 are connected to one of theplural word lines WL₀, . . . , WL_(n). Each drain of the plural memorycells 11 is connected to one of the plural drain lines DL₀, . . . ,DL_(y), DL_(z), and each source of the plural memory cells 11 isconnected to one of the plural source lines SL₀, . . . , SL_(z). TheEPROM also includes circuits such as an address decoder for generatingthe decoded signals DEC₀, . . . , DEC_(n), and a sense amplifier to readthe data stored in the memory cells 11, these not being shown in thefigures.

In each of the memory arrays 10 ₀, . . . , 10 _(n), the drain lines DL₀,. . . , DL_(y), DL_(z) are respectively connected via the NMOStransistors 12 ₀, . . . , 12 _(y1) (or 12 _(y2)), 12 _(z1) (or 12 _(z2))to the write control line 13, to which a drain drive voltage MCD issupplied. In each of the memory arrays 10 ₀, . . . , 10 _(n), ON/OFFcontrol of the even-numbered NMOS transistors 12 ₀, 12 ₂, . . . , 12_(y1), 12 _(z1) is performed by the even number selection signals SE₀, .. . , SE_(n), respectively, and ON/OFF control of the odd-numbered NMOStransistors 12 ₁, 12 ₃, . . . , 12 _(y2), 12 _(z2) is performed by theodd number selection signals SO₀, . . . , SO_(n), respectively.Moreover, in each of the memory arrays 10 ₀, . . . , 10 _(n), the sourcelines SL₀, . . . , SL_(y), SL_(z) are respectively connected to the bitlines BL₀, . . . , BL_(y), BL_(z) via the NMOS transistors 14 ₀, . . . ,14 _(y), 14 _(z) which are ON/OFF controlled by the memory arrayselection signals SS₀, . . . , SS_(n).

The EPROM according to the first embodiment also includes the word linedrive circuits 20 ₀, . . . , 20 _(n) which supply drive signals to eachof the word lines WL₀, . . . , WL_(n), a write control circuit 30A whichsupplies the drain drive voltage MCD to the write control line 13, anddata write circuits 40A₁ and 40A₂ which supply data BLA₁ and BLA₂ (datasupplied to the bit lines BL_(y) and BL_(z) are represented as BLA₃ andBLA₄, respectively) to the bit lines BL₀, . . . , BL_(y), BL_(z) (thedata write circuits 40 ₃ and 40 ₄ supply data BLA₃ and BLA₄ to the bitlines BL_(y) and BL_(z), respectively).

The word line drive circuits 20 ₀, . . . , 20 _(n) have mutuallyidentical constructions. The word line drive circuits 20 ₀, . . . , 20_(n) respectively generate and output word line selection signals to theword lines WL₀, . . . , WL_(n) according to the decoded signals DEC₀, .. . , DEC_(n) supplied from the address decoder. When the decodedsignals DEC₀, . . . , DEC_(n) are at L-level indicating “non-selection”,the word line drive circuits 20 ₀, . . . , 20 _(n) output the groundvoltage GND to the word lines WL₀, . . . , WL_(n). When the decodedsignals DEC₀, . . . , DEC_(n) are at H-level indicating “selection”, theword line drive circuits 20 ₀, . . . , 20 _(n) operate according to theprogram mode signal ^(˜)PGM. During data write, the word line drivecircuits 20 ₀, . . . , 20 _(n) output a program voltage VPP (e.g., 10 V)to the word lines WL₀, . . . , WL_(n), and during data read, output thepower supply voltage VCC (e.g., 4 V) to the word lines WL₀, . . . ,WL_(n), respectively.

The write control circuit 30A includes a reference voltage generatingpart 31, and is controlled by an identical control signal CON to thecontrol signal inputted to the word line drive circuits 20 ₀, . . . , 20_(n). During data write, the control signal CON inputted to the writecontrol circuit 30A is at L-level. When the control signal CON is atL-level, the write control circuit 30A outputs the drain drive voltageMCD (e.g., 6 V) of the voltage VCC+2Vtn (where Vtn is a thresholdvoltage of the NMOS transistor and is approximately 1 V), and when thecontrol signal CON is at H-level, it outputs a drain drive voltage MCDof, for example, 0.8 V.

The data write circuits 40A₁, 40A₂, 40A₃ and 40A₄ have mutuallyidentical constructions. When a data write operation is performed bysetting the program mode signal ^(˜)PGM to L-level, the data writecircuits 40A₁, 40A₂, 40A₃ and 40A₄ output the ground voltage GND or thewrite signals BLA₁ and BLA₂ (or BLA₃ and BLA₄) of the power supplyvoltage VCC from the node N40 depending on whether the input data D₁ andD₂ are L-level or H-level (the input data of the data write circuits40A₃ and 40A₄ is VCC). The data write circuits 40 ₁, 40 ₂, 40 ₃ and 40 ₄are configured in such a way that when a data read operation isperformed by setting the program mode signal ^(˜)PGM to H-level, thenode N40 of the data write circuits 40A₁, 40A₂, 40A₃ and 40A₄ is in ahigh impedance state.

For example, the data write circuit 40A₁ includes an inverter 41 towhich the input data D₁ is supplied, a NOR gate 42 which outputs thenegative logical sum of the output signal of the inverter 41 and theprogram mode signal ^(˜)PGM, and a NOR gate 43 which outputs thenegative logical sum of the output signal of the NOR gate 42 and theprogram mode signal ^(˜)PGM. The data write circuit 40, also includes anNMOS transistor 44 which is connected between the node N40 and groundvoltage GND, and is controlled by the output signal of the NOR gate 43,and an NMOS transistor 45 which is connected between the power supplyvoltage VCC and the node N40, and is controlled by the output signal ofthe NOR gate 42.

The write signals BLA₁ and BLA₂ outputted from the data write circuits40A₁ and 40A₂ are supplied, for example, to the adjacent bit lines BL₀and BL₁ via the transistors 60 a and 60 b selected by the columnselection signals Y₀ and Y₁.

When the logical value ‘L’ is written as data into the memory cell 11selected by the word line WL_(i), the even number selection signalSE_(j) or the odd number selection signal SO_(j), the memory arrayselection signal SS_(j) and the column selection signal Y_(k), the dataD₂ inputted to the data write circuit 40A₂ is at L-level. At this time,the gate voltage Vg of the memory cell 11 is 10 V, the drain voltage Vdis VCC+2Vtn (=6 V), and the source voltage Vs is 0 V. Therefore, in thememory cell 11, a large current I_(d3) flows from the drain DR_(d) tothe source SOU_(cd), and electrons are injected into the floating gate(e.g., in FIG. 5, the floating gate FG_(d)) by the avalanche hot carriergenerated by this current.

On the other hand, when the logical value ‘H’ is written as data intothe memory cell 11 selected by the word line WL_(i), the even numberselection signal SE_(j) or the odd number selection signal SO_(j), thememory array selection signal SS_(j) and the column selection signalY_(k), the data D₂ inputted to the data write circuit 40A₂ is atH-level. At this time, the gate voltage Vg of the memory cell 11 is 10V, the drain voltage Vd is VCC+2Vtn (=6 V), and the source voltage Vs isVCC−Vtn (=3 V). Therefore, in the memory cell 11, only a relativelysmall current flows from the drain to the source (e.g., from the drainDR_(a) to the source SOU_(ab)), and electrons are not injected into thefloating gate (e.g., in FIG. 5, the floating gate FG_(a)) by anavalanche hot carrier.

In the EPROM according to the first embodiment, the two adjacent bitlines BL_(k) and BL_(k+1) are selected simultaneously by the columnselection signal Y_(k). The data (e.g., data BLA₁ and BLA₂) outputtedfrom the data write circuits (e.g., the data write circuits 40A₁ and40A₂) are written respectively into the two memory cells 11 connected tothe selected bit lines BL_(k) and BL_(k+1). In FIG. 1, the memory cells11 a and 11 d are selected by the word line WL₀, the even numberselection signal SE₀, the memory array selection signal SS₀ and thecolumn selection signal Y₀, and the data BLA₁ and BLA₂ aresimultaneously written into the memory cells 11 a and 11 d,respectively. For example, when the memory cell 10 ₀ is selected by thememory array selection signal SS₀, the word line WL₀ is selected by theword line drive circuit 20 _(n), the bit lines BL₀ and BL₁ are selectedby the column selection signal Y₀, and the drain lines DL₀ and DL₂ areselected by the even number selection signal SE₀, a current flows fromthe drain line DL₀ via the memory cell 11 a, source line SL₀, NMOStransistor 14 ₀, and bit line BL₀. As a result, a charge accumulates inthe floating gate of the memory cell 11 a (when it has the logical value‘L’), or does not accumulate in it (when it has the logical value ‘H’).Also, a current flows from the drain line DL₂ via the memory cell 11 d,source line SL₁, NMOS transistor 14 ₁, and bit line BL₁. As a result, acharge accumulates in the floating gate of the memory cell 11 d (when ithas the logical value ‘L’), or does not accumulate in it (when it hasthe logical value ‘H’).

If the program mode signal ^(˜)PGM inputted to the data write circuits40A₁ and 40A₂ is at H-level, the outputs of the NOR gates 42 and 43 areboth at L-level, and the NMOS transistors 44 and 45 are both OFF. As aresult, the outputs of the data write circuits 40A₁ and 40A₂ (i.e., thenode N40) are in a high impedance state. At this time, a current pathfrom the memory cells 11 a, 11 b, 11 c and 11 d to the ground voltageGND does not exist, so when the memory cells 11 a, 11 b, 11 c and 11 dare in the logical value ‘H’ state, the drain lines DL₀, DL₁ and DL₂,the source lines SL₀ and SL₁, and the bit lines BL₀ and BL₁ increase tothe drain drive voltage MCD, i.e., VCC+2Vtn, via the memory cells 11 a,11 b, 11 c and 11 d.

Here, when the logical value ‘H’ is written into the memory cell 11 aand the logical value ‘L’ is written into the memory cell 11 d, theprogram mode signal ^(˜)PGM inputted to the data write circuits 40 ₁ and40 ₂ is at L-level, the write signal BLA₁ outputted from the data writecircuit 40, is at H-level, and the write signal BLA₂ outputted from thedata write circuit 40 ₂ is at L-level. The voltage of the bit line BL₀is then a value of (VCC−Vtn), and the voltage of the bit line BL₁ isGND. At this time, as shown by the arrow I_(d3) in FIG. 5, current flowsfrom the drain DR_(d) to the source SOU_(cd) at the voltage GND,electrons are injected into the floating gate FG_(d) by the avalanchehot carrier and the logical value ‘L’ is written into the memory cell 11d. Also, only a small current flows from the drain DR_(a) to the sourceSOU_(ab) at a voltage (VCC−Vtn) electrons are not injected into thefloating gate FG_(a) by the avalanche hot carrier, and therefore, thelogical value ‘H’ is written into the memory cell 11 a.

Next, a data write operation of the EPROM according to the firstembodiment will be described with reference to FIGS. 2 to 5.

First, at a time to in FIG. 2, the program mode signal ^(˜)PGM and thecontrol signal CON are set to H-level. At the time t₀, the addresssignal ADR which specifies the address to be written is supplied to theaddress decoder (not shown). The address decoder which received theaddress signal ADR selects the memory array selection signal (i.e., oneof the memory array selection signals SS₀, . . . , SS_(n)) for selectingthe memory array (i.e., one of the memory arrays 10 ₀, . . . , 10 _(n))containing the address to be written (i.e., selects H-level). Theaddress decoder which received the address signal ADR supplies thedecode signal (e.g., the decode signal DEC_(n)) for selecting one wordline, e.g., the word line WL₀ in the selected memory array, e.g., memoryarray 10 ₀, (namely, for causing one word line to be at H-level) to theword line drive circuit, e.g., the word line drive circuit 20 _(n).

When the memory array selection signal SS₀ is selected, (i.e., set toH-level), the NMOS transistors 14 ₀, . . . , 14 _(z) of the selectedmemory array 10 ₀ are set to ON, and the source lines SL₀, . . . ,SL_(z) of the selected memory array 10 ₀ are connected to the bit linesBL₀, BL_(z) via the NMOS transistors 14 ₀, . . . , 14 _(z),respectively. On the other hand, the memory arrays 10 ₁, . . . , 10 _(n)which are not selected are electrically isolated from the bit lines BL₀,. . . , BL_(z).

Also, the word line drive circuit 20 _(n) supplies the power supplyvoltage VCC (e.g., 4 V) to the selected word line WL₀ as a word lineselection signal (word line drive voltage), and the power supply voltageVCC is thereby commonly applied to the control gates of the memory cells11 connected to the word line WL₀. The voltage of the word lines WL₀, .. . , WL_(n-1) which are not selected, is ground voltage GND.

The write control circuit 30A also applies a drive voltage of, forexample, 0.8 V to the drain of the selected memory cell 11 as the draindrive voltage (MCD).

At the time t₀, the program mode signal ^(˜)PGM is at H-level. Thevoltages BLA₁, BLA₂, BLA₃ and BLA₄ of the output node N40 from the datawrite circuits 40A₁, 40A₂, 40A₃ and 40A₄ are in the high impedance(H.I.) state, and the bit lines (e.g., the bit lines BL₀ and BL₁) andsource lines (e.g., the bit lines SL₀ and SL₁) which are connected tothe node N40 are also in the high impedance (H.I.) state.

At a time t₁, the program mode signal PGM is changed from H-level toL-level. At this time, the control signal CON is still H-level. If theprogram mode signal ^(˜)PGM is L-level, the output node of the datawrite circuits 40A₁ and 40A₂ will no longer be in a high impedancestate, and will output the ground voltage GND or the drain drive voltageMCD (=0.8 V) corresponding to the input data D₁ and D₂ showing one ofthe logical values ‘H’ or ‘L’. However, at this time, since the datawrite circuits 40A₁ and 40A₂ are not connected to the data bus, theinput data D₁ and D₂ are pulled up to H-level, and the write signalsBLA₁ and BLA₂ become the same (0.8 V) as the drain drive voltage MCD(see FIG. 3). Therefore, not only in the memory cells 11 a and 11 d intowhich data are to be written but also in the adjacent memory cells 11 band 11 c, the voltages of drain and source approximate the groundvoltage GND.

At a time t₂, the input data D₁ (e.g., H-level) and D₂ (e.g., L-level)to be written are supplied to the data write circuits 40A₁ and 40A₂,respectively, via an input/output buffer (not shown). The write datasignal BLA₁ of the data write circuit 40A₁ to which the input data D₁ atH-level was supplied, is still at the drain drive voltage MCD. The writedata signal BLA₂ of the data write circuit 40A₂ to which the input dataD₂ at L-level was supplied, is at the ground voltage GND (see FIG. 4).

At a time t₃, the control signal CON is set to L-level. At this time,the NMOS transistor 21 in the word line drive circuit 20 n is OFF, andthe word line selection signal outputted to the word line WL₀ from ofword line drive circuit 20 _(n) changes from the voltage VCC (=4 V) tothe program voltage VPP (=10 V). Also, the drain drive voltage MCDoutputted from the write control circuit 30A increases from 0.8 V to thevoltage VCC+2Vtn (=6 V) due to the reference voltage generating part 31,and is supplied to the drains of the memory cells 11 a and 11 d in whichthe drain drive voltage MCD was selected and the data write circuits40A₁ and 40A₂ (see FIG. 5). Therefore, the write voltages BLA₁ and BLA₂respectively outputted to the bit lines BL₀ and BL₁ from the data writecircuits 40A₁ and 40A₂ are respectively the drain drive voltage MCD(i.e., VCC+2Vtn) and ground voltage GND corresponding to the input dataD₁ and D₂.

Due to this, in the memory cell 11 d selected by the address signal ADRin which it was specified to write the input data D₂ at L-level, theprogram voltage VPP (=10 V) is applied to the control gate, the draindrive voltage MCD (=6 V) is applied to the drain, and the ground voltageGND (=0 V) is applied to the source, respectively. In this memory cell11 d, the voltage between the control gate and source is a high voltage(10 V), and the voltage between the source and drain is a high voltage(6 V), so some of the electrons (current I_(d3) of FIG. 5) flowingbetween the drain and the source are accelerated by the electric fieldand gain energy, exceed the energy barrier of the gate insulation film,and are injected into the floating gate.

On the other hand, in the memory cell 11 a selected by the addresssignal ADR in which it was specified to write the input data D₁ atH-level, the program voltage VPP (=10 V) is applied to the control gate,the drain drive voltage (MCD) (=6 V) is applied to the drain, and thevoltage VCC−Vtn (=3 V) is applied to the source, respectively. In thiscase, the voltage between the control gate and source is 7 V, and thevoltage between the drain and the source is 3 V, so the energy of theelectrons flowing between the drain and the source is small, and theseelectrons are not injected into the floating gate.

Moreover, at the time t₂ (FIG. 4), the voltage of the drain line DL₁ is0.8 V, and since the charge is very small, at the time t₃-t₄ (FIG. 5), alarge current does not flow from the drain line DL₁, and there are noincorrect writes to memory cells (e.g., 11 b) which are not selected.

At a time t₄, after the time required for data write has elapsed, theprogram mode signal ^(˜)PGM changes from L-level to H-level, and thecontrol signal CON changes from L-level to H-level. Also, the addresssignal ADR is changed over to another address. If the control signal CONis at H-level, the output voltage of the write control circuit 30A willbe 0.8 V. Due to this, the charge accumulated on the write control line13 starts to discharge, and the drain drive voltage MCD falls accordingto a fixed time constant. If the drain drive voltage MCD falls,therefore, the output voltages of the data write circuits 40A₁ and 40A₂will also fall, and the voltage of the bit line BL will also fall.

As described above, in the EPROM according to the first embodiment, bycontrolling the selection signals WL₀, . . . , WL_(n) of the word linesoutputted from the word line drive circuits 20 ₀, . . . , 20 _(n) andthe change-over timing of the drain drive voltage MCD outputted from thewrite control circuit 30A by the program mode signal ^(˜)PGM and thecontrol signal CON which are supplied from outside, the voltage betweenthe source and drain of the adjacent memory cells 11 b and 11 c is madeto approach the ground voltage GND before data is written into thememory cells 11 a and 11 d which were selected for data write. Hence, ahigh voltage is no longer applied between the drain and source of thememory cells 11 b and 11 c which were not selected for data write whendata write is performed, and consequently, there is no incorrect writeof data due to flow of discharge current, and the problem of increase ofthe threshold voltage Vt of the memory cell causing access delay orfluctuations in the operating power supply voltage, can be avoided.

Second Embodiment

FIG. 6 is a diagram schematically showing the construction of an EPROMwhich is a semiconductor memory device according to a second embodimentof the present invention. Those structures in FIG. 6 that are identicalto or correspond to structures in FIG. 1 or FIG. 16 are assignedidentical symbols. Further, FIG. 7 is a signal waveform diagram fordescribing a data write operation of the EPROM according to the secondembodiment.

The EPROM according to the second embodiment differs from the EPROM ofthe first embodiment in that the delay circuit 50 is provided, theprogram mode signal ^(˜)PGM is delayed by the delay circuit 50, and thisdelayed signal is supplied to the word line drive circuits 20 ₀, . . . ,20 _(n) and write control circuit 30A as a control signal CON₁. Thedelay circuit 50 includes components such as a resistance, a capacitorand buffers, and the retardation amount is set to a time intervalcorresponding to the time t₁ to the time t₃ in FIG. 2. As shown in FIG.6, the delay circuit 50, for example, includes inverters 51 a and 51 b,a resistance 52, a capacitor 53, and inverters 54 a and 54 b. Theconstruction of the delay circuit 50 is not limited to that shown inthis figure.

As shown in FIG. 7, the signal waveform when a data write is performedin the EPROM according to the second embodiment is substantiallyidentical to according to the first embodiment if the control signal CONis replaced by the control signal CON₁. However, the control signal CON₁is not at H-level at the time t₁₄, but becomes H-level after apredetermined delay time.

By adding a logic circuit such that the control signal CON₁ becomesL-level at a given time after the program mode signal ^(˜)PGM becomesL-level, and always outputting the H-level control signal CON₁ when theprogram mode signal (^(˜)PGM) is at H-level, a control signal having anidentical timing to the control signal CON₁ of FIG. 7 can be generated.

As described above, the EPROM according to the second embodimentincludes the delay circuit 50 which delays the program mode signal PGMto generate the control signal CON₁, so the same advantage as that ofthe EPROM of the first embodiment can be obtained without requiring theexternal control signal CON. Except for the above point, the secondembodiment is identical to the case of the aforesaid first embodiment.

Third Embodiment

FIG. 8 schematically shows the construction of an EPROM which is asemiconductor memory device according to a third embodiment of thepresent invention. Those structures in FIG. 8 that are identical to orcorrespond to structures in FIG. 1, FIG. 6 or FIG. 16 are assignedidentical symbols. Further, FIG. 9 is a circuit diagram showing theconstruction of a control signal generating circuit 70 of the EPROMaccording to the third embodiment.

The EPROM according to the third embodiment differs from the EPROM ofthe first embodiment in that the control signal generating circuit 70 isprovided, the control signal CON is generated by this control signalgenerating circuit 70, and supplied to the word line drive circuits 20₀, . . . , 20 _(n) and write control circuit 30A. The control signalgenerating circuit 70 generates the control signal CON to be supplied tothe word line drive circuits 20 ₀, . . . , 20 _(n) and write controlcircuit 30A using the signals in the data write circuits 40A₁ and 40A₂.

As shown in FIG. 9, the control signal generating circuit 70 includes aNOR gate 71 which negates the logical sum of a signal S43 outputted froma NOR gate 43 in the data write circuits 40A₁ and 40A₂, and inverters 72and 73 connected to the output node of the NOR gate 71 (these form adelay circuit). The control signal CON is outputted from this delaycircuit.

In the EPROM according to the third embodiment, until the valid inputdata D₁ and D₂ is supplied, i.e. during the time t₀-t₂ in FIG. 2, thesignal S43 outputted from the data write circuits is at L-level.Therefore, a signal S71 outputted from the NOR gate 71 and the controlsignal CON are at H-level.

At the time t₂, when the valid data D₁ and D₂ are supplied, and at leastone of the input data D₁ and D₂ is at L-level, the signal S71 outputtedfrom the NOR gate 71 is at L-level. The signal S71 is delayed by theinverters 72 and 73, and at the time t₃, the control signal CON becomesL-level and is outputted. Except for the above point, the EPROMaccording to the third embodiment is identical to the case of theaforesaid second embodiment.

When the valid input data D₁ and D₂ are both at H-level, the controlsignal CON remains H-level and does not become L-level. Therefore, inthis case, a write operation (i.e., a write of logical value data ‘L’due to charge injection into the floating gate) does not occur in thememory cell. However, the fact that a charge is not injected into thememory cell means that logical value data ‘H’ is written.

As described above, in the EPROM according to the third embodiment, ifat least one of the input data D_(1 and D) ₂ is at L-level, the controlsignal CON is outputted with a predetermined time delay after datainput. Hence, if all the input data is at H-level, a data writeoperation is not performed. Therefore, in the EPROM according to thethird embodiment, in addition to having an identical advantage to thatof the second embodiment, an unnecessary write voltage is not applied,and the stress on the memory cell is mitigated.

Fourth Embodiment

FIG. 10 is a diagram schematically showing the construction of an EPROMwhich is a semiconductor memory according to a fourth embodiment of thepresent invention. Those structures in FIG. 10 that are identical to orcorrespond to structures in FIG. 1, FIG. 6, FIG. 8 or FIG. 16 areassigned identical symbols. Further, FIG. 11 is a circuit diagramshowing the construction of a data write circuit 40C of the EPROMaccording to the fourth embodiment.

In the EPROM according to the fourth embodiment, the construction of thedata write circuit 40C differs from the EPROM of the first embodiment.In the data write circuit 40C of the fourth embodiment, an NMOStransistor 47 of which the transconductance g_(m) is much smaller thanthat of the NMOS transistor 45, is connected between the node N40 of thedata write circuit 40A₁ shown in FIG. 1 and the ground voltage GND, andthe output signal of the NOR gate 42 is supplied to the gate of the NMOStransistor 47.

In the EPROM which uses this data write circuit 40C, instead of thecontrol signal CON supplied to the word line drive circuits 20 ₀, . . ., 20 _(n), and write control circuit 30A, the program mode signal^(˜)PGM is used.

FIG. 12 is a signal waveform diagram for describing a data writeoperation of the EPROM according to the fourth embodiment. Further, FIG.13 to FIG. 15 are diagrams (No. 1-No. 3) for describing a data writeoperation of the EPROM according to the fourth embodiment.

When a data write operation is not performed, the program mode signalPGM is set to H-level.

When data write starts, at a time t₂₀ in FIG. 12, the address signal ADRwhich specifies an address to be written is supplied to the addressdecoder, and from this address decoder, for example, the memory arrayselection signal SS₀ and even number selection signal SE₀ are suppliedto the memory array 10 ₀, and the decode signal DEC₀ which selects theword line WL₀ is supplied to the word line drive circuit 20 ₀. As aresult, the selected memory array 10 ₀ is connected to the bit linesBL₀, . . . , BL_(y), BL_(z), and the memory arrays 10 ₁, . . . , 10 _(n)which were not selected are electrically isolated from these bit linesBL₀, . . . , BL_(y), BL_(z). The selection signal of the power supplyvoltage VCC is also applied from the word line drive circuit 20 ₀ to thecontrol gate of the memory cell connected to the selected word line WL₀.Further, the drain drive voltage MCD is applied to the drain of theselected memory cell 11, and the source is connected to the data writecircuit 40C via the source lines SL₀, . . . , SL_(x), SL_(z) and bitlines BL₀, . . . , BL_(y), BL_(z) (see FIG. 13).

At a time t₂₁, the program mode signal ^(˜)PGM is at L-level, and a datawrite operation starts. The output node of the data write circuit 40C isno longer in a high impedance state, and becomes ground voltage GND orthe drain drive voltage MCD (at this time, 0.8 V) with respect to theinput data D₁ and D₂. However, at this time the data write circuit 40Cis not connected to the data bus, so the input data D₁ and D₂ are atH-level.

On the other hand, the word line selection signal outputted from theword line drive circuit 20 ₀ to the word line WL₀ increases to theprogram voltage VPP (=10 V) Also, the drain drive voltage MCD outputtedfrom the write control circuit 30A increases from 0.8 V to the voltageVCC+2Vtn (=6 V), and this drain drive voltage MCD is supplied to thedrains DR_(a) and DR_(d) of the selected memory cells 11 a and 11 d andthe data write circuit 40C.

At this time, in the data write circuit 40C, the NMOS transistor 47 isON, so the voltage of the node N40 is set to the voltage VCC−Vtn (=3 V)by the transconductance g_(m) ratio between this NMOS transistor 47 andthe NMOS transistor 45. Therefore, the write voltages BLA₁ and BLA₂outputted from the data write circuit 40C to the bit lines BL₀ and BL₁increase only to the voltage VCC−Vtn (see FIG. 14).

At a time t₂₂, the input data D₁ (e.g., L-level) and D₂ (e.g., H-level)which are to be written are respectively supplied to the data writecircuit 40C from the data bus via an input/output buffer (not shown).Due to this, the write data signal BLA₁ of the data write circuit 40C towhich the L-level input data D₁ was supplied effectively becomes theground voltage GND. On the other hand, the write data signal BLA₂ of thedata write circuit 40C to which the H-level input data D₂ was supplied,remains the voltage VCC−Vtn. In this state, a charge is injected intothe floating gate FG_(d) by a current I_(d4) and the logical value ‘L’is written into the memory cell 11 d, whereas the logical value ‘H’ iswritten into the memory cell 11 a without injecting a charge into thefloating gate FG_(a) (see FIG. 15).

At a time t₂₃, after a time required for data write has elapsed, theprogram mode signal ^(˜)PGM becomes H-level, the address signal ADRchanges over to another address, and the data write operation isterminated.

As described above, in the EPROM according to the fourth embodiment, theNMOS transistor 47 is added between the node N40 and ground voltage GND,and the write data signal BLA₁ does not increase above the voltageVCC−Vtn. Therefore, before writing data to the memory cells 11 a and 11d to which data is to be written, the voltage of the drain and source ofthe adjacent memory cells 11 b and 11 c can be made equal to or lessthan the power supply voltage VCC. In this way, a high voltage is notapplied between the drain and the source of the memory cells 11 b and 11c to which data is not to be written during a data write, and anidentical effect to that of the second embodiment is obtained.

The invention being thus described, it will be obvious that the same maybe varied in many ways. Such variations are not to be regarded as adeparture from the spirit and scope of the invention, and all suchmodifications as would be obvious to one skilled in the art are intendedto be included within the scope of following claims.

1. A semiconductor memory device comprising: plural word lines; pluraldrain lines; plural source lines; a memory array including plural memorycells formed from a field effect transistor having a gate, a drain, asource and a floating gate, said gate of each of said plural memorycells being connected to any of said plural word lines, said drain ofeach of said plural memory cells being connected to any of said pluraldrain lines, said source of each of said plural memory cells beingconnected to any of said plural source lines; a data write circuit whichreceives a first control signal and write data and supplies a sourcedrive voltage to said source line when data is written into said memorycell; a write control circuit which receives a second control signalsupplied later than said first control signal and supplies a drain drivevoltage based on said second control signal to said drain line when datais written into said memory cell; and a word line drive circuit whichreceives an address signal and said second control signal, and suppliesa word line drive voltage based on said second control signal to saidword line selected according to said address signal; wherein said writecontrol circuit outputs said drain drive voltage at a high level fordata write via said drain line to said memory cell selected by said wordline drive circuit when a data write operation is commanded by saidsecond control signal, and outputs said drain drive voltage at a lowlevel when a data write operation is not commanded by said controlsignal, and said data write circuit generates a write voltagecorresponding to a logical value of data to be written into saidselected memory cell based on said drain drive voltage outputted fromsaid write control circuit, and supplies said write voltage as saidsource drive voltage via said source line to said selected memory cellwhen a data write operation is commanded by said first control signal.2. The semiconductor memory device according to claim 1, furthercomprising a delay circuit which delays said first control signal togenerate said second control signal.
 3. The semiconductor memory deviceaccording to claim 1, further comprising a control circuit generatingcircuit which generates and outputs said second control signal when adata write operation is commanded by said first control signal and saiddata write operation is performed to accumulate charge in said floatinggate by said data to be written into said selected memory cell.
 4. Asemiconductor memory device comprising: plural word lines; plural drainlines; plural source lines; a memory array including plural memory cellsformed from a field effect transistor having a gate, a drain, a sourceand a floating gate, said gate of each of said plural memory cells beingconnected to any of said plural word lines, said drain of each of saidplural memory cells being connected to any of said plural drain lines,said source of each of said plural memory cells being connected to anyof said plural source lines; a data write circuit which receives acontrol signal and write data and supplies a source drive voltage tosaid source line when data is written into said memory cell; a writecontrol circuit which receives said control signal and supplies a draindrive voltage based on said control signal to said drain line when datais written into said memory cell; and a word line drive circuit whichreceives an address signal and said control signal and supplies a wordline drive voltage based on said second control signal to a word lineselected according to said address signal; wherein said write controlcircuit outputs said drain drive voltage at a high level for data writevia said drain line to said memory cell selected by said word line drivecircuit when a data write operation is commanded by said control signal,and outputs said drain drive voltage at a low level when a data writeoperation is not commanded by said control signal, and said data writecircuit generates a write voltage corresponding to a logical value ofdata to be written into said selected memory cell based on said draindrive voltage outputted from said write control circuit, and suppliessaid write voltage as said source drive voltage via said source line tosaid selected memory cell when a data write operation is commanded bysaid first control signal.
 5. The semiconductor memory device accordingto claim 4, wherein said data write circuit includes: a first transistorconnected between a first output node of said write control circuit anda second output node which outputs said write voltage; a secondtransistor connected between ground voltage and said second output node,conduction state of said second transistor being controlled by a signalaccording to a logical value which is an inverse of said logical valueof said data to be written; and a third transistor connected betweenground potential and said second output node, conduction state of saidthird transistor being controlled by a signal according to said logicalvalue of said data to be written.
 6. A semiconductor memory devicecomprising: plural word lines; plural drain lines; plural source lines;a memory array including plural memory cells formed from a field effecttransistor having a gate, a drain, a source and a floating gate, saidgate of each of said plural memory cells being connected to any of saidplural word lines, said drain of each of said plural memory cells beingconnected to any of said plural drain lines, said source of each of saidplural memory cells being connected to any of said plural source lines;a data write circuit which receives a first control signal set to any offirst and second control voltages and write data corresponding to any offirst and second logical values, and supplies a source drive voltagebased on said write data to said source line when data is written intosaid memory cell; a write control circuit which receives a secondcontrol signal set to any of third and fourth control voltages, andsupplies a drain drive voltage based on said second control signal tosaid drain line when data is written into said memory cell; and a wordline drive circuit which receives an address signal and said secondcontrol signal, and supplies a word line drive voltage based on saidsecond control signal to said word line selected according to saidaddress signal when data is written into said memory cell; wherein, whendata is written into said memory cell, said first control signal ischanged over from said first control voltage to said second controlvoltage, and said second control signal is changed over from said thirdcontrol voltage to said fourth control voltage at a time which is laterthan a time at which said first control signal is changed over to saidsecond control voltage, said write control circuit sets said drain drivevoltage to a first drive voltage when said second control signal is saidthird control voltage, and sets said drain drive voltage to a seconddrive voltage higher than said first drive voltage when said secondcontrol signal is said fourth control voltage, said word line drivecircuit sets said selected word line to a third drive voltage when saidsecond control signal is said first control voltage, and sets saidselected word line to a fourth drive voltage higher than said thirddrive voltage when said second control signal is said fourth controlvoltage, and said data write circuit sets said source drive voltage to avoltage lower than said drain drive voltage from when said first controlsignal is changed over to said second control voltage to when saidsecond control signal is changed over to said fourth control voltage,and sets said source drive voltage to any of a fifth drive voltagehigher than said drain drive voltage and a sixth drive voltage lowerthan said drain drive voltage according to a logical value of said writedata while said second control signal is said fourth control voltage. 7.A semiconductor memory device, comprising: plural word lines; pluraldrain lines; plural source lines; a memory array including plural memorycells formed from a field effect transistor having a gate, a drain, asource and a floating gate, said gate of each of said plural memorycells being connected to any of said plural word lines, said drain ofeach of said plural memory cells being connected to any of said pluraldrain lines, said source of each of said plural memory cells beingconnected to any of said plural source lines; a data write circuit whichreceives a first control signal and write data corresponding to any offirst and second logical values, and supplies a source drive voltagebased on said write data to said source line when data is written intosaid memory cell; a delay circuit which delays said first control signalset to any of first and second control voltages to generate a secondcontrol signal; a write control circuit which receives a second controlsignal set to any of third and fourth control voltages, and supplies adrain drive voltage based on said second control signal to said drainline when data is written into said memory cell; and a word line drivecircuit which receives an address signal and said second control signal,and supplies a word line drive voltage based on said second controlsignal to said word line selected according to said address signal whendata is written into said memory cell; wherein, when data is writteninto said memory cell, said write control circuit sets said drain drivevoltage to a first drive voltage when said second control signal is saidthird control voltage, and sets said drain drive voltage to a seconddrive voltage higher than said first drive voltage when said secondcontrol signal is said fourth control voltage, said word line drivecircuit sets said selected word line to a third drive voltage when saidsecond control signal is said third control voltage, and sets saidselected word line to a fourth drive voltage higher than said thirddrive voltage when said second control signal is said fourth controlvoltage, and said data write circuit sets said source drive voltage to avoltage lower than said drain drive voltage from when said first controlsignal is changed over to said second control voltage to when saidsecond control signal is changed over to said fourth control voltage,and sets said source drive voltage to any of a fifth drive voltagehigher than said drain drive voltage and a sixth drive voltage lowerthan said drain drive voltage according to a logical value of said writedata while said second control signal is said fourth control voltage. 8.A semiconductor memory device, comprising: plural word lines; pluraldrain lines; plural source lines; a memory array including plural memorycells formed from a field effect transistor having a gate, a drain, asource and a floating gate, said gate of each of said plural memorycells being connected to any of said plural word lines, said drain ofeach of said plural memory cells being connected to any of said pluraldrain lines, said source of each of said plural memory cells beingconnected to any of said plural source lines; a data write circuit whichreceives a first control signal set to any of first and second controlvoltages and write data corresponding to any of first and second logicalvalues, and supplies a source drive voltage based on said write data tosaid source line when data is written into said memory cell; a writecontrol circuit which receives a second control signal set to any ofthird and fourth control voltages, and supplies a drain drive voltagebased on said second control signal to said drain line when data iswritten into said memory cell; a word line drive circuit which receivesan address signal and said second control signal, and supplies a wordline drive voltage based on said second control signal to said word lineselected according to said address signal when data is written into saidmemory cell; and a control signal generating circuit which changes oversaid second control signal to said fourth control voltage, when data iswritten into said memory cell, said first control signal is said secondcontrol voltage, and a charge is accumulated in said floating gate bydata to be written into said selected memory cell; wherein said writecontrol circuit sets said drain drive voltage to a first drive voltagewhen said second control signal is said third control voltage, and setssaid drain drive voltage to a second drive voltage higher than saidfirst drive voltage when said second control signal is said fourthcontrol voltage, said word line drive circuit sets said selected wordline to a third drive voltage when said second control signal is saidthird control voltage, and sets said selected word line to a fourthdrive voltage higher than said third drive voltage when said secondcontrol signal is said fourth control voltage, and said data writecircuit sets said source drive voltage to a voltage lower than saiddrain drive voltage from when said first control signal is changed overto said second control voltage to when said second control signal ischanged over to said fourth control voltage, and sets said source drivevoltage to any of a fifth drive voltage higher than said drain drivevoltage and a sixth drive voltage lower than said drain drive voltageaccording to a logical value of said write data while said secondcontrol signal is said fourth control voltage.
 9. A semiconductor memorydevice comprising: plural word lines; plural drain lines; plural sourcelines; a memory array including plural memory cells formed from a fieldeffect transistor having a gate, a drain, a source and a floating gate,said gate of each of said plural memory cells being connected to any ofsaid plural word lines, said drain of each of said plural memory cellsbeing connected to any of said plural drain lines, said source of eachof said plural memory cells being connected to any of said plural sourcelines; a data write circuit which receives a control signal set to anyof first and second control voltages and write data corresponding to anyof first and second logical values, and supplies a source drive voltagebased on said write data to said source line when data is written intosaid memory cell; a write control circuit which receives said controlsignal, and supplies a drain drive voltage based on said control signalto said drain line when data is written into said memory cell; and aword line drive circuit which receives an address signal and saidcontrol signal, and supplies a word line drive voltage based on saidcontrol signal to said word line selected according to said addresssignal when data is written into said memory cell; wherein, when data iswritten into said memory cell, said control signal changes over fromsaid first control voltage to said second control voltage; said writecontrol circuit sets said drain drive voltage to a first drive voltagewhen said control signal is said first control voltage, and sets saiddrain drive voltage to a second drive voltage higher than said firstdrive voltage when said control signal is said second control voltage,said word line drive circuit sets said selected word line to a thirddrive voltage when said control signal is said first control voltage,and sets said selected word line to a fourth drive voltage higher thansaid third drive voltage when said control signal is said second controlvoltage, and said data write circuit generates a write voltagecorresponding to said logical value of said data to be written into saidselected memory cell using said drain drive voltage outputted from saidwrite control circuit when said source drive voltage is changed over tosaid second control voltage of said control signal, and supplies saidwrite voltage as said source drive voltage to said selected memory cellvia said source line.